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rev. prh information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the proper ty of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. 4-channel, software selectable true bipolar input, 12-bit plus sign adc preliminary technical data AD7324* features ? 12-bit plus sign sar adc ? true bipolar input ranges ? software selectable input ranges 10v, 5v, 2.5v, 0 to 10v ? 1 msps throughput rate ? four analog input channels with channel sequencer ? single ended, true differential and pseudo differential analog input capability ? high analog input impedance ? low power:- 26 mw max ? full power signal bandwidth: 7 mhz ? internal 2.5 v reference ? high speed serial interface ? power down modes ? 16-lead tssop package ? i cmos tm process technology ? for eight and two channel equivalent devices see ad7328 and ad7322 respectively. general description the AD7324 is a 4-channel, 12-bit plus sign successive approximation adc. the adc has a high speed serial interface that can operate at throughput rates up to 1 msps. the AD7324 can accept true bipolar analog input signals. the AD7324 has four software selectable inputs ranges, 10v, 5v, 2.5v and 0 to 10v. each analog input channel can be independently programmed to one of the four input ranges. the analog input channels on the AD7324 can be programmed to be single-ended, true differential or pseudo differential. the AD7324 contains a 2.5v internal reference. the AD7324 also allows for external reference operation. if a 3v reference is applied the ref in/out pin the AD7324 can accept a true bipolar 12v analog input. minimum v dd and v ss supplies of 12v are required for the 12v input range. * protected by u.s. patent no. 6,731,232 functional block diagram figure 1. product highlights 1. the AD7324 can accept true bipolar analog input signals, 10v, 5v, 2.5v and 0 to 10v unipolar signals. 2. the four analog inputs can be configured as 4 single-ended inputs, 2 true differential, 2 pseudo differential or 3 pseudo differential inputs. the AD7324 has high impedance analog inputs. 3. the AD7324 features a high speed serial interface. throughput rates up to 1 msps can be achieved on the AD7324. 4. low power, 26 mw at maximum throughput rate of 1 msps. device number number of bits number of channels ad7328 12-bits plus sign 8 ad7322 12-bits plus sign 2 i cmos tm process technology for analog systems designers within industrial/instrumentation eq uipment oems who need high performance ics at higher-voltage l evels, i cmos is a technology platform that enables the development of analog ics capable of 30v and operating at +/- 15v supplies while allowing dramatic reductions in power consumption and package size, and increased ac and dc performance.
AD7324 preliminary technical data rev. prh| page 2 of 21 table of contents AD7324specifications.................................................................. 3 absolute maximum ratings............................................................ 6 pin functional descriptions ....................................................... 7 terminology ...................................................................................... 8 theory of operation.....................................................................9 AD7324 registers ........................................................................... 12 serial interface ................................................................................ 20 outline dimensions .................................................................. 21 revision history revision prh: preliminary version
AD7324 preliminary technical data rev. prh | page 3 of 21 AD7324specifications 1 table 1. unless otherwise noted, v dd = + 12v to +16.5v, v ss = -12v to C16.5v, v cc = 2.7v to 5.25v, v drive = 2.7v to 5.25v, v ref = 2.5v internal/external, f sclk = 20 mhz, f s = 1 msps t a = t max to t min parameter specification unit s test conditions/comments dynamic performance f in = 50 khz sine wave signal to noise ratio (snr) 2 76 db min differential mode 72 db min single-ended /pseudo differential mode signal to noise + distortion (sinad) 2 75 db min differential mode 71.5 db min single-ended/pseudo differential mode total harmonic distortion (thd) 2 -80 db max peak harmonic or spurious noise (sfdr) 2 -80 db max intermodulation distortion (imd) 2 f a = 40.1 khz, f b = 41.5 khz second order terms -88 db typ third order terms -88 db typ aperature delay 2 10 ns max aperature jitter 2 50 ps typ common mode rejection (cmrr) 2 tbd db typ channel-to-channel isolation 2 -80 db typ f in = 400 khz full power bandwidth 2 7 1.5 mhz typ mhz typ @ 3 db @ 0.1 db dc accuracy resolution 12+sign bits integral nonlinearity 2 1.5 lsb max differential nonlinearity 2 0.95 lsb max guaranteed no missing codes to 13-bits offset error 3 8 lsb max unipolar range with straight binary output coding offset error match 2 0.5 lsb max gain error 2 6 lsb max gain error match 2 0.6 lsb max positive full-scale error 2 3 lsb max bipolar range with twos complement output coding positive full scale error match 2 0.6 lsb max bipolar zero error 2 8 lsb max bipolar zero error match 2 0.5 lsb max negative full scale error 2 4 lsb max negative full scale error match 2 0.5 lsb max analog input input voltage ranges (programmed via range register) 10v 5v 2.5v 0 to 10v volts v dd = +10v min , v ss = -10v min, v cc = 2.7v to 5.25v v dd = +5v min, v ss = -5v min, v cc = 2.7v to 5.25v v dd = +5v min, v ss = - 5v min, v cc = 2.7v to 5.25v v dd = +10v min, v ss = 0 v min, v cc = 2.7v to 5.25v see table 5 dc leakage current 10 na max input capacitance 12 pf typ wh en in track, 10v range 15 pf typ when in track, 5v, 0 to 10v range 20 pf typ when in track, 2.5v range 3 pf typ when in hold reference input/output input voltage range +2.5 to +3v v min to max input dc leakage current 1 a max input capactiance 20 pf typ reference output voltage 2.49/2.51 vmin/max reference temperature coefficient 25 ppm/c max 10 ppm/c typ reference output impedance 25 ? typ
AD7324 preliminary technical data rev. prh| page 4 of 21 parameter specification unit s test conditions/comments logic inputs input high voltage, v inh 2.4 v min input high voltage, v inl 0.8 v max v cc = 4.75 to 5.25 v 0.4 v max v cc = 2.7 to 3.6 v input current, i in 1 a max v in = 0v or v cc input capacitance, c in 3 10 pf max logic outputs output high voltage, v oh v drive - 0.2v v min i source = 200 a output low voltage, v ol 0.4 v max i sink = 200 a floating state leakage current 1 a max floating state output capacitance 3 10 pf max output coding straight natural binary coding bit set to 1 in control register twos complement coding bit set to 0 in control register conversion rate conversion time 800 ns max 16 sclk cycles with sclk = 20 mhz track-and-hold acquisition time 200 ns max sine wave input 200 ns max full scale step input throughput rate 1 msps max see serial interface section power requirements digital inputs = 0v or v cc v dd 4 12v/+16.5v v min/max see table 5 v ss 4 -12v/16.5v v min/max see table 5 v cc 2.7v / 5.25v v min/max see table 5 v drive 2.7v/5.25v v min/max normal mode i dd 300 a max v dd = +16.5v i ss 370 a max v ss = -16.5v i cc 2 ma max v cc = 5.25v auto-standby mode f sample = tbd i dd tbd a max i ss tbd a max i cc 1.6 ma typ auto-standby mode f sample = tbd i dd tbd a max i ss tbd a max i cc 1 ma typ full shutdown mode i dd 0.9 a max i ss 0.9 a max i cc 0.9 a max sclk on or off power dissipation normal mode 26 mw max v dd = +16.5v, v ss = -16.5v, v cc = 5.25v, full shutdown mode 35 w max v dd = +16.5v, v ss = -16.5v, v cc = 5.25v, notes 1 temperature ranges as follows: -40c to +85c 2 see terminology 3 guaranteed by characterization 4 functional from v dd = +4.75v and v ss = -4.75v specifications subject to change without notice.
AD7324 preliminary technical data rev. prh | page 5 of 21 timing specifications table 2. unless otherwise noted, v dd = +12v to + 16.5v, v ss = -12v to C16.5v, v cc =2.7v to 5.25, v drive =2.7v to 5.25, v ref = 2.5v internal/external, t a = t max to t min parameter limit at t min , t max unit description f sclk 10 khz min 20 mhz max t convert 16t sclk ns max t sclk = 1/f sclk t quiet 50 ns max minimum time between end of serial read and next falling edge of cs t 1 10 ns min minimum cs pulse width t 2 10 ns min cs to sclk setup time t 3 20 ns max delay from cs until d out three-state disabled t 4 tbd ns max data access time after sclk falling edge. t 5 0.4t sclk ns min sclk low pulsewidth t 6 0.4t sclk ns min sclk high pulsewidth t 7 10 ns min sclk to data valid hold time t 8 25 ns max sclk falling edge to d out high impedance 10 ns min sclk falling edge to d out high impedance t 9 tbd ns min din set-up time prior to sclk falling edge t 10 5 ns min din hold time after sclk falling edge 1 s max power up from auto standby tbd s max power up from full shutdown/auto shutdown mode figure 2. serial interface timing diagram
AD7324 preliminary technical data rev. prh | page 6 of 21 absolute maximum ratings table 3. t a = 25c, unless otherwise noted v dd to agnd, dgnd -0.3 v to +16.5 v v ss to agnd, dgnd +0.3 v to C16.5 v v cc to agnd, dgnd -0.3v to +7v v drive to v cc -0.3 v to v cc + 0.3v agnd to dgnd -0.3 v to +0.3 v analog input voltage to agnd v ss -0.5v to v dd + 0.5v digital input voltage to dgnd -0.3 v to +7 v digital output voltage to gnd -0.3 v to v drive +0.3v ref in to agnd -0.3 v to v cc +0.3v input current to any pin except supplies 2 10ma operating temperature range -40c to +85c storage temperature range -65c to +150c junction temperature +150c tssop package ja thermal impedance 143 c/w jc thermal impedance 45 c/w pb-free temperature, soldering reflow 260(+0)c esd tbd
AD7324 preliminary technical data rev. prh | page 7 of 21 pin functional descriptions 16 15 14 13 12 11 9 top view (not to scale) 8 1 2 3 4 7 6 5 AD7324 din sclk refin/out v ss dgnd dout v in 1 v in 2 10 v drive v in 3 v in 0 agnd dgnd v dd figure 3. AD7324 pin configuration tssop table 4. AD7324 pin function descriptions pin mnemonic pin number description sclk 16 serial clock. logic input. a se rial clock input provides the sc lk used for accessing the data from the AD7324. this clock is also used as the clock source for the conversion process. d out 14 serial data output. the conversi on output data is suppl ied to this pin as a serial data stream. the bits are clocked out on the falling edge of the sclk input and 16 sclks are required to access the data. the data stre am consists of one leading zero followed by two channel identification bits, followed by th e sign bit followed by the 12 bits of conversion data. the data is provided msb first. see the serial interface section. cs 1 chip select. active low logic input. this inp ut provides the dual function of initiating conversions on the AD7324 and frames the serial data transfer. din 2 data in. data to be written to the on-chip register s is provided on this in put and is clocked into the register on the falling edge of sclk. see register section. agnd 4 analog ground. ground reference point for all an alog circuitry on the AD7324. all analog input signals and any external reference signal sh ould be referred to this agnd voltage. ref in/ ref out 5 reference input/ reference output pin. the on-chi p reference is available on this pin for use external to the AD7324. alternat ivley, the internal reference ca n be disabled and an external reference applied to this input. when usin g the AD7324 with an external reference, the internal reference must be disabled via the co ntrol register. the nominal reference voltage is 2.5 v, which appears at the pin. a 470 nf decoupling capacitor sgould be placed on the reference pin. v cc 12 analog supply voltage, 2.7 v to 5.25 v. this is the supply voltage for the adc core on the AD7324. this supply should be decoupled to agnd. v dd 11 positive power supply voltage. this is the posi tive supply voltage for the analog input section. v ss 6 negative power supply voltage. this is the ne gavtive supply voltage for the analog input section. v drive 13 the voltage applied to this pin determines th e voltage at which the serial interface operates. dgnd 3,15 this is the digital ground connection. vin0-vin3 7,8,9,10 analog input 0 through analog input 3. the an alog inputs are multiplexed into the on-chip track-and-hold. the analog input channel for conversion is selected by programming the channel address bits, add1 through add0, in the control register. the inputs can be configured as 4 single-ended inputs, 2 true differential input pairs, 2 pseudo differential inputs or 3 pseudo differential in puts. the configuration of the analog inputs is selected by programming the mode bits, mode1 and mode0, in the control register. the input range on each input channel is controlled by programmin g the range register. input ranges of 10v, 5v, 2.5v and 0 to 10v can be selected on each analog input channel. see register section.
AD7324 preliminary technical data rev. prh | page 8 of 21 terminology differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. integral nonlinearity this is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale, a point 1 lsb below the first code transition, and full scale, a point 1 lsb above the last code transition. offset code error this applies to straight binary output coding. it is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, i.e., agnd + 1 lsb. offset error match this is the difference in offset error between any two input channels. gain error this applies to straight binary output coding. it is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (i.e., 4 x vref C 1 lsb, 2 x v ref C1 lsb, v ref C1 lsb) after the offset error has been adjusted out. gain error match this is the difference in gain error between any two input channels channels. bipolar zero code error this applies when using twos complement output coding and a bipolar analog input. it is the deviation of the midscale transition (all 1s to all 0s) from the ideal v in voltage, i.e., agnd - 1 lsb. bipolar zero code error match this refers to the difference in bipolar zero code error between any two input channels. positive full scale error this applies when using twos complement output coding and any of the bipolar analog input ranges. it is the deviation of the last code transition (011110) to (011111) from the ideal ( +4 x v ref - 1 lsb, + 2 x v ref C 1 lsb, + v ref C 1 lsb) after the bipolar zero code error has been adjusted out. positive full scale error match this is the difference in positive full scale error between any two input channels. negative full scale error this applies when using twos complement output coding and any of the bipolar analog input ranges. this is the deviation of the first code transition (10000) to (10001) from the ideal (i.e., - 4 x v ref + 1 lsb, - 2 x v ref + 1 lsb, - v ref + 1 lsb) after the bipolar zero code error has been adjusted out. negative full scale error match this is the difference in negative full scale error between any two input channels. track-and-hold acquisition time the track-and-hold amplifier returns into track mode after the fifteenth sclk falling edge. track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within 1/2 lsb, after the end of conversion. signal to (noise + distortion) ratio this is the measured ratio of signal to (noise + distortion) at the output of the a/d converter. the signal is the rms amplitude of the fundamental. noise is the sum of all non-fundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. the theoretical signal to (noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by: signal to (noise + distortion) = (6.02n + 1.76) db thus for a 13-bit converter, this is 80.02 db. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. for the AD7324 it is defined as: 1 2 6 2 5 2 4 2 3 2 2 log 20 ) ( v v v v v v db thd + + + + = where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to fs/2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it will be a noise peak. channel-to-channel isolation channel-to-channel isolation is a measure of the level of crosstalk between any two channels. it is measured by applying a full-scale, 400 khz sine wave signal to all unselected input channels and determining how much that signal is attenuated in
preliminary technical data AD7324 rev. prh| page 9 of 21 the selected channel with a 50 khz signal. the figure given is the worst-case across all eight channels for the AD7324. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with non-linearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. intermodulation distortion terms are those for which neither m nor n are equal to zero. for example, the second order terms include (fa + fb) and (fa C fb), while the third order terms include (2fa + fb), (2fa C fb), (fa + 2fb) and (fa C 2fb). the AD7324 is tested using the ccif standard where two input frequencies near the top end of the input bandwidth are used. in this case, the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. as a result, the second and third order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dbs. psr (power supply rejection) variations in power supply will affect the full-scale transition but not the converters linearity. power supply rejection is the maximum change in full-scale transition point due to a change in power supply voltage from the nominal value. see typical performance curves. theory of operation circuit information the AD7324 is a fast, 4-channel, 12-bit plus sign, bipolar input, serial a/d converter. the AD7324 can accept bipolar input ranges that include 10v, 5v, 2.5v, it can also accept 0 to 10v unipolar input range. a different analog input range can be programmed on each analog input channel via the on-chip range register. the AD7324 has a high speed serial interface that can operate at throughput rates up to 1 msps. the AD7324 requires v dd and v ss dual supplies for the high voltage analog input structure. these supplies must be equal to or greater than the analog input range. see table 5 for the minimum requirements on these supplies for each analog input range. the AD7324 requires a low voltage 2.7v to 5.25 v v cc supply to power the adc core. table 5. reference and supply requirements for each analog input range selected analog input range (v) reference voltage (v) full scale input range(v) av cc (v) minimum v dd /v ss (v) 2.5 10 3/5 10 10 3.0 12 3/5 12 2.5 5 3/5 5 5 3.0 6 3/5 6 2.5 2.5 3/5 5 2.5 3.0 3 3/5 5 2.5 0 to 10 3/5 +10/agnd 0 to 10 3.0 0 to 12 3/5 +12/agnd in order to meet the specified performance specifications when the AD7324 is configured with the minimum v dd and v ss supplies for a chosen analog input range the throughput rate should be decreased from the maximum throughput range. see typical performance curves. the analog inputs can be configured as either 4 single-ended inputs, 2 true differential inputs, 2 pseudo differential inputs or 3 pseudo differential inputs. selection can be made by programming the mode bits, mode0 and mode1, in the control register. the serial clock input accesses data from the part but also provides the clock source for each successive approximation adc. the AD7324 has an on-chip 2.5 v reference. however the AD7324 can also work with an external reference. on power up the external reference operation is the default option. if the internal reference is the preferred option the user must write to the reference bit in the control register to select the internal reference operation. the AD7324 also features power-down options to allow power saving between conversions. the power-down modes are selected by programming the on-chip control register, as described in the modes of operation section. converter operation the AD7324 is a successive approximation analog-to-digital converter, based around two capacitive dacs. figure 4 and figure 5 show simplified schema tics of the adcs in single ended mode during the acquisition and conversion phase, respectively. figure 6 and figure 7 show simplified schematics of the adcs in differential mode during acquisition and conversion phase, respectively. the adc is comprised of control logic, a sar, and a capacitive dac. in figure 4 (the acquisition phase), sw2 is closed and sw1 is in position a, the comparator is held in a balanced condition, and the sampling capacitor array acquires the signal on the input.
AD7324 preliminary technical data rev. prh| page 10 of 21

figure 4. adc acquisition phase(single ended) when the adc starts a conversion (figure 5), sw2 will open and sw1 will move to position b, causing the comparator to become unbalanced. the control logic and the charge redistribution dac is used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. when the comparator is rebalanced, the conversion is complete. the control logic generates the adc output code

figure 5. adc conversion phase(single ended) figure 6 shows the differential configuration during the acquisition phase. for the conversion phase, sw3 will open, sw1 and sw2 will move to position b, see figure 7. the output impedances of the source driving the vin+ and vin- pins must be matched; otherwise the two inputs will have different settling times, resulting in errors.

figure 6. adc differential config uration during acquisition phase

figure 7. adc differential config uration during conversion phase output coding the AD7324 default output coding is set to twos complement. the output coding is controlled by the coding bit in the control register. to change the output coding to straight binary coding the coding bit in the control register must be set. when operating in sequence mode the output coding for each channel in the sequence will be the value written to the coding bit during the last write to the control register. transfer functions the designed code transitions occur at successive integer lsb values (i.e., 1 lsb, 2 lsb, and so on). the lsb size is dependant on the analog input range selected. table 6. lsb sizes for each analog input range input range full scale range/8192 lsb size 10v 20v/8192 2.441 mv 5v 10v/8192 1.22 mv 2.5v 5v/8192 0.61 mv 0 to 10v 10v/8192 1.22 mv the ideal transfer characteristic for the AD7324 when twos complement coding is selected is shown in figure 8, and the ideal transfer characteristic for the AD7324 when straight binary coding is selected is shown in figure 9. figure 8 twos complement transfer characteristic (bipolar ranges) figure 9. straight binary transfer characteristic (bipolar ranges) analog input the analog inputs of the AD7324 may be configured as single- ended, true differential or pseudo differential via the control register mode bits as shown table 9 of the register section. the AD7324 can accept true bipolar input signals. on power up the analog inputs will operate as 4 single-ended analog input channels. if true differential or pseudo differential is required, a write to the control register is necessary to change this configuration after power up.
preliminary technical data AD7324 rev. prh| page 11 of 21 figure 10 shows the equivalent analog input circuit of the AD7324 in single-ended mode. figure 11 shows the equivalent analog input structure in differential mode. the two diodes provide esd protection for the analog inputs. d d v dd c2 r1 vin0 v ss c1 figure 10. equivalent analog input circuit-(single ended) d d v dd c2 r1 vin+ v ss c1 d d v dd c2 r1 vin- v ss c1 figure 11. equivalent analog input circuit-(differential) care should be taken to ensure the analog input never exceeds the v dd and v ss supply rails by more than 300 mv. this will cause the diodes to become forward biased and start conducting into either the v dd or v ss rails. these diodes can conduct up to 10 ma without causing irreversible damage to the part. the capacitor c1, in figure 10 and figure 11 is typically 4 pf and can primarily be attributed to pin capacitance. the resistor r1, is a lumped component made up of the on-resistance of the input multiplexer and the track-and-hold switch. the capacitor c2, is the sampling capacitor, its capacitance will vary depending on the analog input range selected. track-and-hold section the track-and-hold on the analog input of the AD7324 allows the adc to accurately convert an input sine wave of full scale amplitude to 12-bit plus sign accuracy. the input bandwidth of the track-and-hold is greater than the nyquist rate of the adc, the AD7324 can handle frequencies up to 7 mhz. the track-and-hold enters its tracking mode on the 15 th sclk falling edge after the cs falling edge. the time required to acquire an input signal will depend on how quickly the sampling capacitor is charged. with zero source impedance 200 ns will be sufficient to acquire the signal to the 13-bit level. the acquisition time required is calculated using the following formula: t acq = 10 x ((r source + r) c) where c is the sampling capacitance and r is the resistance seen by the track-and-hold amplifier looking back on the input. for the AD7324, the value of r will include the on-resistance of the input multiplexer. the value of r is typically 300 ? . r source should include any extra source impedance on the analog input. the AD7324 enters track on the fifteenth sclk falling edge. when running the AD7324 at a throughput rate of 1 msps with a 20 mhz sclk signal the adc will have approx. 1 sclk period plus t 8 plus the quiet time, t quiet , in order to acquire the analog input signal. the adc goes back into hold on the cs falling edge. typical connection diagram figure 12 shows a typical connection diagram for the AD7324. in this configuration the agnd pin is connected to the analog ground plane of the system. the dgnd pin is connected to the digital ground plane of the system. the analog inputs on the AD7324 can be configured to operate in single ended, true differential or pseudo differential mode. the AD7324 can operate with either the internal or an external reference. in figure 12, the AD7324 is configured to operate with the internal 2.5v reference. a 470 nf decoupling capacitor is required when operating with the internal reference. the v cc pin can be connected to either a 3v or a 5v supply voltage. the v dd and v ss are the dual supplies for the high voltage analog input structures. the voltage on these pins must be equal to or greater than the highest analog input range selected on the analog input channels, see table 5 for more information. the v drive pin is connected to the supply voltage of the microprocessor. the voltage applied to the v drive input controls the voltage of the serial interface. figure 12. typical connection diagram
AD7324 preliminary technical data rev. prh | page 12 of 21 AD7324 registers the AD7324 has three-programmable registers, the control register , sequence register , and the range register . these registers are write only registers. addressing these registers a serial transfer on the AD7324 consists of 16 sclk cycles. the three msbs on the din line during this 16 sclk transfer are dec oded to determine which register is addressed during the serial transfer. the three msbs consists of the write bit, register select 1 b it and register select 2 bit. the register select bits are used to determine which of the four on-board registers is selected. the write bit wi ll determine if the data on the din line following the register select bits will be loaded into the addressed register or not. if the write bi t is 1 the bits will be loaded into the register addressed by the register select bits. if the write bit is a 0 the data on the din will not be loaded into any register. table 7. decoding register select bits and write bit. write register select1 register select2 comment 0 0 0 data on the din line during this serial transfer will be ignored 1 0 0 this combination selects the control regi ster. the subsequent 12 bits will be loaded into the control register. 1 0 1 this combination selects the range register. the subsequent 8 bits will be loaded into the range register. 1 1 1 this combination selects the sequence register. the subsequent 8 bits will be loaded into the sequence register. control register the control register is used to select the analog input configur ation, reference, coding, power mode etc. the control register is a write only 12-bit register. data loaded on the din line corresponds to the AD7324 configuration for the next conversion. data should be loaded into the control register after the range register and the sequence register has been initialized, that is if the sequen ce register is being used. the bit functions of the control register are outlined in table 8. control register (the power-up status of all bits is 0) table 8. control register msb lsb write register select 1 register select 2 dontc add1 add0 mode1 mode0 pm1 pm0 coding ref seq1 seq2 zero 0 bit mnemonic comment 12 dontc dont care. the value written to this bit of the control regist er is a dont care, i.e., it doesnt matter if the bit is 0 or 1. 11,10 add1, add0 these two channel address bits are used to select the analog input channel for the next conversion if the sequencer is not being used. if the sequencer is being us ed, these two channel address bits are used to select the final channel in a consecutive sequence. 9, 8 mode1, mode0 these two mode bits are used to sele ct the configuation on the four an alog input pins. they are used in conjunction with the channel address bits. on the AD7324 the analog inputs can be configured as either 4 single ended inputs, 2 fully differenti al inputs, 2 pseudo differential inputs or 3 pseudo differential inputs. see table 9 7,6 pm1, pm0 power management bits. th ese two bits are used to select di fferent power mode options. table 10. 5 coding this bit is used to select the type of output coding the AD7324 will use for the next conversion result. if the
preliminary technical data AD7324 rev. prh| page 13 of 21 coding = 0 then the output coding wi ll be 2s complement. if coding = 1, then the output coding will be straight binary. when operating in sequence mode th e output coding for each channel will be the value written to the coding bit during the last write to the control register. 4 ref reference bit. this bit is used to en able or disable the internal reference. if this ref = 0 then the external reference will be enabled and used for the next conversion and the internal reference wi ll be disabled. if ref = 1 then the internal reference will be used for the next conversion. when operating in sequence mode the reference used for each channel will be the value writte n to the ref bit during the last write to the control register. 3,2 seq1/seq2 the sequence 1 and sequence 2 bits are used to control the operation of the sequencer. see table 11. 1 zero a zero must be written to this bi t to ensure correct operation of the AD7324. table 9. analog input configuration selection table 10. power mode selection mode1 =1, mode0 = 1 mode1 = 1, mode0 =0 mode1 = 0, mode0 =1 mode1 =0, mode0 =0 channel address bits 3 pseudo differential i/ps 4 fully differential i/ps 2 pseudo different ial i/ps four-single ended i/ps add1 add0 vin+ vin- vin+ vin- vin+ vin- vin+ vin- 0 0 vin0 vin3 vin0 vin1 vin0 vin1 vin0 agnd 0 1 vin1 vin3 vin0 vin1 vin0 vin1 vin1 agnd 1 0 vin2 vin3 vin2 vin3 vin2 vin3 vin2 agnd 1 1 not allowed vin2 vin3 vin2 vin3 vin3 agnd pm1 pm0 description 1 1 full shutdown mode, in this mode all internal circuitry on the AD7324 is powered down. information in the control register is retained when the AD7324 is in full shutdown mode. 1 0 auto shutdown mode, the AD7324 will enter full shut down at the end of each conversion when the control register is updated. all internal circuitry is powered down in full shutdown. 0 1 auto standby mode, in this mode all internal circuitry is powered down excluding the internal reference. the AD7324 will enter auto standby mode at the end of the conversion after the control register is updated. 0 0 normal mode, all internal circuitry is powered up at all times.
AD7324 preliminary technical data rev. prh | page 14 of 21 table 11. sequencer selection the sequence register the sequence register on the AD7324 is a 4-bit write only register. each of the four analog input channels has one correspondi ng bit in the sequence register. to select a channel for inclusion in the sequence set the corresponding channel bit to 1 in the sequenc e register. table 12. sequencer register msb lsb write register select 1 register select 2 vin0 vin1 vin2 vin3 0 0 0 0 0 0 0 0 0 range register the range register to used to select one analog input range per analog input channel. range. it is an 8-bit write only register , with two dedicated range bits for each of the analog input channels from channel 0 to channel3 . there are four analog input ranges to c hoose from, 10v, 5v, 2.5v, 0 to 10v. a write to the range register is selected by setting the write bit to 1 and the register sel ect bits to 0, 1. once the initial write to the range register occurs the AD7324 automatically configures the analog inputs from channel 0 to cha nnel 3 to the appropriate range, as indicated by the range register, each time any one of these analog input channels is selected. the 10v input range is selected by default on each analog input channel. see table 13. table 13. range register msb lsb write reg select 1 reg select2 vin0a vin0b vin1a vin1b vin2a vin2b vin3a vin3b 0 0 0 0 0 seq1 seq2 sequence type 0 0 the channel sequencer is not used. the analog cha nnel selected by programming the add1 and add0 bits in the control register selects the next channel for conversion. 0 1 this selects the sequence of channels as previously programmed in the sequence register for conversion. the AD7324 will start converting on the lowest channel in th e sequence. it converts the channels in ascending order. if uninterrupted the AD7324 will keep converting the sequence. the range for each channel selected will default to the ranges previously written into the range registers. 1 0 this configuration is used in conjunction with the channel address bits in the control register. it allows continuous conversions on a consecutive sequence of cha nnels, from channel 0, up to and including, a final channel selected by the channel addr ess bits in the control register. the range for each channel will default to the ranges previously wri tten into the range registers. 1 1 the channel sequencer is not used. the analog cha nnel selected by programming the add1 and add0 bits in the control register selects the next channel for conversion.
AD7324 preliminary technical data rev. prh | page 15 of 21 vinxa vinxb description 0 0 this combination selects the 10v input range on analog input x. 0 1 this combination selects the 5v input range on analog input x. 1 0 this combination selects the 2.5v input range on analog input x. 1 1 this combination selects the 0 to 10v input range on analog input x.
AD7324 preliminary technical data rev. prh | page 16 of 21 sequencer operation

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figure 13. programmable sequence flow chart the AD7324 can be configured to automatically cycle through a number of selected channels using the on-chip sequence register and the seq1 and seq2 bits in the control register. figure 13 shows how to program the AD7324 register in order to operate in sequence mode. after power up all of the three on-chip registers will contain default values. each analog input will have a default input range of 10v. if different analog input ranges are required then a write to the range register is required, this is shown in the first serial transfer in figure 13. this initial serial transfer is only necessary if input ranges other than the default ranges are required. after the analog input ranges are configured a write to the sequence register is necessary to select the channels to be included in the sequence. once the channels for the sequence have been selected, the sequence can be initiated by writing to the control register and setting the seq1 =0, seq2 = 1. the AD7324 will continue to convert through the selected sequence uninterrupted provided the sequence register remains unchanged and seq1 = 0 and seq2 = 1 in the control register. if during a sequence a change to one of the range registers is required, it is first necessary to stop the sequence by writing to the control register and setting seq1 = 0 and seq2 = 0. next the write to the range register can be completed to change the required range. then the previously selected sequence can be initiated again by writing to the control register and setting seq1 = 0 and seq2 = 1, the adc will then convert on the first channel in the sequence. the AD7324 can be configured to convert a sequence of consecutive channels, see figure 14. this sequence will begin by converting on channel 0 and end with a final channel as selected by bits add1 to add0 in the control register. in this configuration there is no need for a write to the sequence register. to operate the AD7324 in this mode set seq1 = 1 and seq2 = 0 and select the final channel in the sequence by programming bits add1 to add0 in the control register. once the control register is configured to operate the AD7324 in this mode the din line can be held low or the write bit can be set to 0, the AD7324 will then continue operating in this
preliminary technical data AD7324 rev. prh| page 17 of 21 mode. to return to traditional multichannel operation a write to the control register is necessary, setting seq1 = 0 and seq2 =0. when the seq1 and seq2 are both set to 0 or when both are set to 1 the AD7324 is configured to operate in traditional multichannel mode where a write to the channel address bits, add1 to add0, in the control register selects the next channel for conversion. in traditional multichannel mode it is necessary to write to the AD7324 in each serial transfer to select the next channel for conversion. however if a number of conversions are required on one channel then one write to the control register is necessary to select this channel via the channel address bits, add1, add0. the din line can then be held low or the write bit set to zero during the require number of conversions.

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AD7324 preliminary technical data rev. prh| page 18 of 21 reference the AD7324 can operate with either the internal 2.5v on-chip reference or an externally applied reference. the internal reference is selected by setting the ref bit in the control register to 1. on power up the ref bit will be 0, selecting the external reference for the AD7324 conversion. for external reference operation the ref in /ref out pin should be decoupled to agnd with a 470 nf capacitor. the internal reference circuitry consists of a 2.5v band gap reference and a reference buffer. when operating the AD7324 in internal reference mode the 2.5v internal reference is available at the ref in /ref out pin. when using the AD7324 with the internal reference the refin/refout pin should be decoupled to agnd using a 470 nf cap. it is recommended that the internal reference be buffered before applying it else where in the system. the AD7324 is specified for a 2.5v to 3v reference range. when a 3v reference is selected the ranges will be, 12v, 6v, 3v and 0 to 12v. for these ranges the v dd and v ss supply must be equal to or greater than the max analog input range selected. on power up if the internal reference operation is required for the adc conversion, a write to the control register is necessary to set the ref bit to 1. during the control register write the conversion result from the first init ial conversion will be invalid. the reference buffer will require tbd us to power up and charge the 470 nf decoupling cap, during the power up time the conversion result from the adc will be invalid.
AD7324 preliminary technical data rev. prh | page 19 of 21 modes of operation the AD7324 has a number of different modes of operation. these modes are designed to provide flexible power management options. these options can be chosen to optimize the power dissipation/throughput rate ratio for the differing application requirements. the mode of operation of the AD7324 is controlled by the power management bits, pm1 and pm0, in the control register as detailed in table 10 .the default mode is normal mode, where all internal circuitry is fully powered up. normal mode (pm1 = pm0 = 0) this mode is intended for the fastest throughput rate performance, the AD7324 is fully powered up at all times. figure 15 shows the general diagram of operation of the AD7324 in normal mode. the conversion is initiated on the falling edge of cs and the track and hold will enter hold mode as described in the serial interface section. the data on the din line during the 16 sclk transfer will be loaded into one of the on-chip registers, provided the write bit is set. the register is selected by programming the register select bits, see tabl e 7 of the register section. figure 15. normal mode the AD7324 will remain fully powered up at the end of the conversion provided both pm1 and pm0 contain 0 in the control register. sixteen serial clock cycles are required to complete the conversion and access the conversion result. at the end of the conversion cs may idle high until the next conversion or may idle low until sometime prior to the next conversion. once the data transfer is complete, another conversion can be initiated after the quiet time, t quiet , has elapsed. full shutdown mode (pm1 = pm0 = 1) in this mode all internal circuitry on the AD7324 is powered down. the part retains information in the registers during full shut down. the AD7324 remains in full shutdown mode until the power managements bits in the control register, pm1 and pm0, are changed. if a write to the control register occurs while the part is in full shut down mode, with the power management bits, pm1 and pm0 set to 0, normal mode, the part will begin to power up on the cs rising edge. to ensure the AD7324 is fully powered up, t power up , should elapse before the next cs falling edge. auto shutdown mode (pm1 = 1, pm0 = 0) once the auto shutdown mode is selected the AD7324 will automatically enter shutdown at the end of each conversion. the AD7324 retains information in the registers during shutdown. the track-and-hold is in hold during shutdown. on the falling cs edge, the track-and-hold that was in hold during shutdown will return to track. the power-up from auto shutdown is tbd s in this mode the power consumption of the AD7324 is greatly reduced with the part entering shutdown at the end of each conversion. when the control registers is programmed to move into auto shutdown mode, it does so at the end of the conversion. auto standby mode (pm1 = 0, pm0 =1) in auto standby mode portions of the AD7324 are powered down but the on-chip reference remains powered up. the reference bit in the control register should be 0 to ensure the on-chip reference is enabled. this mode is similar to auto shutdown but allows the AD7324 to power up much faster, allowing faster throughput rates to be achieved. the AD7324 will enter standby at the end of the conversion. the part retains information in the registers during standby. the AD7324 will remain in standby until it receives a cs falling edge. the adc will begin to power up on the cs falling edge. on this cs falling edge the track-and-hold that was in hold mode while the part was in standby will return to track. wake- up time from standby is 1 s. the user should ensure that 1 s has elapsed before attempting a valid conversion. when running the AD7324 with the maximum 20 mhz sclk, one dummy conversion of 16 x sclks is sufficient to power up the adc. this dummy conversion effectively halves the throughput rate of the AD7324, with every second conversion result being a valid result. once auto standby mode is selected, the adc can move in and out of the low power state by controlling the cs signal.
AD7324 preliminary technical data rev. prh | page 20 of 21 serial interface figure 16 shows the timing diagram for the serial interface of the AD7324. the serial clock applied to the sclk pin provides the conversion clock and also controls the transfer of information to and from the AD7324 during a conversion. the cs signal initiates the data transfer and the conversion process. the falling edge of cs puts the track-and-hold into hold mode, take the bus out of three-state and the analog input signal is sampled at this point. once the conversion is initiated it will require 16 sclk cycles to complete. the track-and-hold will go back into track on the 15th sclk falling edge. on the sixteenth sc lk falling edge, the dout line will return to three-state. if the rising edge of cs occurs before 16 sclk cycles have elapsed, the conversion will be terminated, the dout line will return to three-state, and depending on when the cs signal is brought high the addressed register may or may not be updated. data is clocked into the AD7324 on the sclk falling edge. the three msb on the din line are decoded to select which register is being addressed. the control register is an eleven bit register, if the control register is addressed by the three msb, the data on the din line will be loaded into the control on the 15 th sclk falling edge. if the sequence register or the range register is addressed the data on the din line will be loaded into the addressed register on the 11 th sclk falling edge. conversion data is clocked out of the AD7324 on each sclk falling edge. data on the dout line will consist of two leading zeros, two channel identifier bits and the 12-bit plus sign conversion result. the channel identifier bits are used to indicate which channel the conversion result corresponds to. figure 16. serial interface timing diagram (control register write)
AD7324 preliminary technical data rev. prh | page 21 of 21 outline dimensions 16-lead thin shrink small outline (tssop) (ru-16) ordering guide AD7324 products temperature package package description package outline AD7324bruz C40c to +85c tssop ru-16 eval-AD7324cb 1 evaluation board eval-control brd2 2 controller board notes 1 this can be used as a stand-alone evaluation board or in conjunction with the eval-control board for evaluation/demonstration purposes. 2 this board is a complete unit allowing a pc to control and communicate with all analog devices evaluation boards ending in th e cb designators. to order a complete evaluation kit, the particular adc evaluation board, e .g., eval-AD7324cb, the eval-control b rd2, and a 12v transformer must be ordered. see relevant evaluation board technical note fo r more information. esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge with out detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.

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